boards for 93000 tester with GPDPS P/N E7002-66404.

tester.

Tester, Frequency 330 MHz, Pin Count 256, Vector Memory 4M, GPDPS 8, Workstation Model J210XC, HP-UX 10.20 10.20, SmarTest Version 5.5.4+1.

SOC Tester Manipulator for Large Test Head (product number E6979E).

tester.

tester.

WDA High Speed Digitzer Sampling Rate: 1Msps to 41Msps Resolution: 12-bit Bandwidth @-3 dB (characteristic data): 100 MHz @±0.5 V range, filter through Pin counts per module: 8 single-ended or 4 differential (one at a time) Waveform capture memory: 512 k samples Input Range: ±2 V, ±1 V, ±0.5 V, ±0.25 V.

Tester.

mixed signal tester IP Option consists of: (Qty 4) LVDS cards for image capture (Qty 4) image capture computers with frame grabber hardware - model IA IPM020 InterAction illuminator model IA-OPT150W.

mixed signal tester.

RF Tester 512pin head w/256 pins total 16M vector memory/pin (2m/14m) (Qty 3) Quad GPDPS device power supply instruments (12 supplies total) CE Certified Integrated MicroHandling GP Manipulator Chiller included Model: E 2760FA Type: SC01-28/5-8.0 HP C3750 System Computer RF Option (Kestrel): 6gig modulated RF source E4438C Wide bandwidth digitizer E6406C Signal Processor E9825A Microwave Synthesizer E6432 RFIC IQ Analog Analog DC/DC.

mixed signal tester.

mixed signal tester Liquid cooling unit E2760DA Hose kit testhead / cooler E2760DA PCI based WKSTN GPIO E2790C SOC Series system E6970S SOC Series P-model base system E6978BB SOC Series 960PIN general purpose E6979E DUT interface SOC Series S960PINS E6980C (Qty 8) SOC Series DC power unit digital E6989A (Qty 31) SOC Series model P600 16 channel board 14M E6996CC SOC Series model P600 16 channel board 112M E6996CG (Qty 32) POGO cables E6998B (Qty 2) general purpose DPS E7002AA High current DSP E7002C Extended Diagnostics BD E7002CF SOC Series Cal Matrix E7008A DUT Board E7010C Docking adapter plates w/ Handler Plates E7016A Controller software bundle E7036AA 512MB memory expansion E7037AA STD workstation controller bundle E7038C SOC Series Smartest E7050A DDS cartridge E7050AA Smartest system manuals E7050AB SOC Series scan test E7052A.

Small Head Tester Min 240 IO channels Min DPS x 2: 8 channels Min P600 PE boards VRAM 28 Meg x 8: 128 channels Includes: Main frame Manipulator Small test head Cooling unit: E2760D Workstation HP C3600 LCD monitor, Tape drive OS Unix 11i, Smart Test Rev. 4.3.9 De-installed Installation available As-is, where-is Pictures were taken prior to de-installation by our supplier's engineers.

SOC test system Configuration: Testhead: TH_8CC DUT I/F: SOC Multiport feature is ON Number of installed I/O channels: 352 Number of licensed I/O channels : 352 | HW | Vectors | Channel | Model | SRAM | VRAM | 10101-12216 | P600 | 2M | 14M | Number of analog boards: 5 217: RFD Rev. 0 219: RFC Rev. 0 221: RFB Rev. 0 228: MCA Rev. 0 901: RFA Rev. 0 Multi-channel analog board configuration: Slot # | Unit Number | Type MCA228 | 2281-2288 | MESA Number of DPS channels : 24 DPS 1 : 8 (MSDPS) Rev.A DPS 2 : 8 (MSDPS) Rev.A DPS 3 : 8 (MSDPS) Rev.A De-installed Can be inspected.

test system (Qty 2) P1000 boards 512 pin head 208 pins stuffed 600 MHz.

test system Large Test Head, 1024 TH 8 Card Cage 384 IO Channels Memory 56M (Qty 3) GDPS (Qty 1) HVDPS (4 channels per card) (Qty 6) Analog Boards (2x WDA, 2x WDB, 1x WGD, 1x WGA) Includes Chiller unit and Calibration unit Linux workstation Unit is powered up and has had recent NIST Calibration Can be inspected Copyright 1988-2008 by Verigy **************************************** *** SmarTest Software for *** *** Verigy 93000 *** *** Series Test System *** **************************************** Base s/w rev. 6.3.4 , Dec 4 2008 Firmware s/w rev. 6.3.4 , Dec 4 2008 Hp83000 job: 0; environment key: ':0.0' Verigy 93000 ONLINE Testhead: TH_8CC DUT I/F: SOC_8GROUP Multiport feature is ON Noise Figure feature is OFF Number of installed I/O channels: 384 Number of licensed I/O channels : 384 | HW | Vectors | Channel | Model | SRAM | VRAM | others -------------+---------+------+------+----------------------- 10101-12416 | P600 | 2M | 56M | Number of analog boards: 6 225: WDA Rev. 0 226: WDB Rev. 0 227: WDA Rev. 0 228: WDB Rev. 0 230: WGD Rev. 0 232: WGA Rev. 0 Device Power Supply (DPS) configuration: Number of DPS channels : 16 -----+----------+----------+-------------------------------- DPS | Type | Channels | Comments -----+----------+----------+-------------------------------- 1 | GPDPS | 4 | 2 | GPDPS | 4 | 3 | GPDPS | 4 | 8 | HVDPS | 4 | Configuring Tester Hardware... done User : ag_maint Device : demo on '/user/ag_maint/' Dev_tech.: cmos Dev_model: P600 (act) Dev_license_file: None, model file used for licensing Loading will be done through import filter '/opt/hp93000/soc/com/lbin/hp83_import' Prior to save '/opt/hp93000/soc/com/lbin/hp83_presave' will be run After save '/opt/hp93000/soc/com/lbin/hp83_postsave' will be run JStart Ready! Now starting eclipse. Starting SmarTest WorkCenter... SmarTest WorkCenter Ready! Configuration: GLOBAL # # ::= P | C | Ce | MCU # # ::= 256 | 512 | 1024 # # ::= F330 | SOC | EXHIBITION # ::= # Pay-Per-Use Device File (needed for serial adapter only) # ### IOCHANNEL # # , ::= # ::= 101..132, 201..232 # ::= 01..16 # ::= | | | SPLIT | HVD # ::= NP2500 | NP2000 | NP1700 | # P1000 | P800 | P600 | P330 | # C400 | C200 | # C400e | C200e | # MCU # ::= SRAM = [] # Size of SRAM (sequencer memory) # ::= SDRAM = [] # Size of SDRAM (vector memory), not for MCU # ::= # ::= K | M | G # SPLIT = Flag for Split IO channels, only for P1000, P800, P600, P330 # HVD = Flag for High Voltage driver channels, only for MCU # ### ANALOGBOARD # # , ::= # ::= PPS | HVP | WDA | WDB | ... # ::= # ::= Total number of core (instrument) # ::= Extra info about the board such as options etc. # (ex. STD | MINI_ME | MULT | ...) # # * information is/(is not) required based on . # * information is optional. # ### SOC_CABLING # # ::= WGC | TIA | ... # ::= Board number # ::= Core number # ::= # ::= Total number of channels for each core (instrument) # # * SOC_CABLING entries are used only for analog module which uses external # instrument. # * This entry specifies core number, and device id for corresponding # board number. # ### SOC_INSTRUMENTS # # ::= Name of logical (GPIB) bus connected to instrument # ::= # ::= IP address of instrument | netmask | IP address of gateway # # * SOC_INSTRUMENT entries are used only for analog module which uses # external instrument. # * This entry specifies instrument name, and GPIB addr for corresponding # analog module and device id. # Note that instrument name is CASE SENSITIVE. Because it's used to # identify instrument by hardware control software. # * The GPIB address is local to the bus identified by . # All buses must be defined in the INTERFACE_SECTION. # Instruments connected to the same must have different # GPIB addresses. # ### AMC # # , ::= Cage number of testhead # # * For 512pin SOC system, specify cage 1 for digital modules, # and cage 2, and 4 for analog modules. # * For 1024pin SOC system, specify cage 5 for digital modules, # cage 2, 4, 6, and 8 for analog modules. # * For NP2500 systems specify AMC with option=NP2500, # card cage ranging from 1-8 independed of other non-NP2500 AMCs # ### INTERFACE_SECTION # # ::= Name of logical bus # ::= GPIB # ::= "[/]" # # * The identifies a GPIB interface and its driver. # # * For interfaces controlled by SICL, the # is optional (if given, it must be 'sicl') and the # must correspond to a symbolic name in the SICL hardware # configuration file (/etc/opt/sicl/hwconfig.cf). # # Examples: "hpib", "sicl/hpib2" # # * For VXI-11 (LAN-to-GPIB) interfaces, the # must be 'vxi11' and the syntax for is # # ::= / # # Example: "vxi11/192.168.0.100/hpib" # # * Bus names must be unique. All names are case sensitive. # ### ETC # # ::= PPS_OLD_CAL | PPS_EXD_CAL | PPS_AUT_CAL # # * PPS_OLD_CAL ... measures voltage, gain, and offset. # needs DVM 3458A and writes the results on std__ # * PPS_EXD_CAL ... measures voltage, gain, and offset. # needs DVM 3458A and writes the results on EEPROM # * PPS_AUT_CAL ... measures only offset with system PMU # ### DPS # # , ::= 1..8 # ::= GPDPS | HVDPS | HCDPS | EDPS # ### OSCILLOSCOPE # # ::= # ::= HP54[] # ::= 0..9 # ::= A..Z # # * OSCILLOSCOPE entries are for information only. They aren't used # by the software. # #################################################################################################### # Example model file: GLOBAL tester = P # P | C | Ce | MCU # testhead = BIG # 256 | 512 | 1024 testhead = TH_8CC dut_interface = SOC # F330 | SOC | EXHIBITION hpib_interface = vxi11/192.168.0.103/gpib0 # hpib | vxi11/192.168.0.100/gpib0 # ppu_device = /dev/tty1p0 OCHANNEL 10101-12416: model = P600, sram = 2M, sdram = 56M # 20101-23216: sram = 2M, sdram = 14M ANALOGBOARD 225: type = WDA, core=1 226: type = WDB, core=1 227: type = WDA, core=1 228: type = WDB, core=1 # 229: type = WGC, core=2 # 230: type = WGB, core=1 230: type = WGD, core=1 # 231: type = WGA, core=1 232: type = WGA, core=1 # 216: type = WDE, core=2 # 209: type = TIA # 210: type = SPA # 211: type = WDA # 212: type = WDB # 213: type = WGC # 214: type = WGB # 214: type = WGD # 215: type = WGA # 210-211: type = PPS # 214: type = HVP # 901: type = RFA, config=N236xA0AAA # 924: type = CMA # 925: type = CMB # 926: type = CMB # 927: type = CMC # 928: type = PGA # 929: type = DAA # 930: type = EAA # 931: type = PGA # 932: type = SWA SOC_CABLING # TIA : board=225, core=1, devid=1, devchan=1 # TIA : board=225, core=2, devid=2, devchan=1 # TIA : board=209, core=1, devid=3, devchan=1 # TIA : board=209, core=2, devid=4, devchan=1 # WGC : board=229, core=1, devid=1, devchan=1 # WGC : board=229, core=2, devid=2, devchan=1 # WGC : board=213, core=1, devid=3, devchan=1 # WGC : board=213, core=2, devid=4, devchan=1 # CMA : board=924, core=1, devid=1, devchan=1 # CMB : board=925, core=1, devid=1, devchan=1 # CMB : board=926, core=1, devid=2, devchan=1 # CMC : board=927, core=1, devid=1, devchan=1 # PGA : board=928, core=1, devid=2, devchan=1 # DAA : board=929, core=1, devid=1, devchan=1 # EAA : board=930, core=1, devid=1, devchan=1 # PGA : board=931, core=1, devid=1, devchan=1 # SWA : board=932, core=1, devid=1, devchan=1 SOC_INSTRUMENTS # SOCGPIB: type=TIA, devid=1, addr=17, name=DTS2077 # SOCGPIB: type=TIA, devid=2, addr=18, name=DTS2077 # SOCGPIB: type=TIA, devid=3, addr=19, name=DTS2077 # SOCGPIB: type=TIA, devid=4, addr=20, name=DTS2077 # SOCGPIB: type=WGC, devid=1, addr=22, name=AWG610, option=192.168.0.2|255.255.255.0|192.168.0.1 # SOCGPIB: type=WGC, devid=2, addr=23, name=AWG610, option=192.168.0.3|255.255.255.0|192.168.0.1 # SOCGPIB: type=WGC, devid=3, addr=24, name=AWG610, option=192.168.0.4|255.255.255.0|192.168.0.1 # SOCGPIB: type=WGC, devid=4, addr=25, name=AWG610, option=192.168.0.5|255.255.255.0|192.168.0.1 # SOCGPIB: type=CMA, devid=1, addr=7, name=AgilentE4426B # SOCGPIB: type=CMB, devid=1, addr=8, name=AgilentE4422B # SOCGPIB: type=CMB, devid=2, addr=9, name=AgilentE4422B # SOCGPIB: type=CMC, devid=1, addr=10, name=Agilent33250A # SOCGPIB: type=PGA, devid=2, addr=11, name=Agilent86130A # SOCGPIB: type=DAA, devid=1, addr=12, name=Agilent86100A # SOCGPIB: type=EAA, devid=1, addr=13, name=Agilent86130A # SOCGPIB: type=PGA, devid=1, addr=13, name=Agilent86130A # SOCGPIB: type=SWA, devid=1, addr=14, name=Agilent8760C AMC # 1: type = E4426B, level = 0, address = 15 # 5: type = E4426B, level = 0, address = 15 # 2: type = E4425B, level = 6, address = 16 # 4: type = E4425B, level = 6, address = 16 # 6: type = E4425B, level = 6, address = 16 # 8: type = E4425B, level = 6, address = 16 # 1-8: type = E4425B, level = 6, address = 28, option = NP2500 INTERFACE_SECTION # SOCGPIB : iftype=GPIB, addr=hpib2 ETC # NFSSERVER : ipaddr=192.168.0.1 # CALIBRATION : pps_cal_mode = PPS_EXD_CAL # ACPOWER : FREQ = 50 DPS 1-3: type = GPDPS # 4-6: type = GPDPS # 7: type = EDPS 8: type = HVDPS OSCILLOSCOPE # 1: type = HP54503A, address = 8.

Tester.

Tester.

Tester.

test system.

Tester HP93K P1000 (384pin, 3GPDPS, STH) Currently stored in a warehouse.

Flash memory wafer test system, parts machine.

Logic Tester Currently stored in a warehouse.

Logic Testers Currently stored in a warehouse.

testers, part machines.

Flash memory wafer test system, parts machine.

Flash memory wafer test system.

Flash memory wafer test system.

Logic Tester Currently stored in a warehouse.

Flash Memory Test System 36 Site Modules 144 Total Test Sites 4608 Total I/O 432 Total DPS 144 Total PMU 36 Total ADC Module: PPC Test Site Controller PAPG Algorithmic Pattern Generator PPS-12 Programmable Power Supply PE32 Pin Electronics Channels 8M Buffer Memory 128M Error Catch Ram STD-PEFPIF Front Plane Interface Bitmap Tool Option Testhead Support: 1 Standard Manipulator 4 Clock Module (TH) 8 DC/DC Board 4 Communications Board System Support: 4 AC/DC Module 1 SSIC 1 PDU Workstation Monitor 2006 vintage.

Test System General Slots for Instruments 8 512 channel System Power Input Power 100V – 240V; 50-60Hz; 1.5Kw Single phase power Utility Power for DUT Board +15V/-15V 0.5A +5V 3A +12V 1A Utility Relay Control Number 8 on every TRG Max using 64 simultaneously Output Current Max. 100mA per Channel, Max 6A totally Software Workstation OS Windows XP professional Stylus User interface FlopPlot Analysis software for scan testing Operating Tools Prober & Handler GPIB Resource Pin Channels 512 Input, Output or I/O PRG 1 total 12 DPS 4x2.5A 8x 200mA PMU 64 channel share 1 pmu Per each 64 pins TRG FMU (FREQUENCY MEASUREMENT UNIT) (Option software license) 1 per TRG Each TRG can contain an optionally integrated frequency counter that can be used to measure a continuous input signal frequency on any of the data pins. Measurement accuracy is <.02% for frequencies from 33 to 200MHz Timing Sub-system Data Period Range (parallel and serial) 20ns - 635ns Clock Period range (Clock Format) 10ns - 635ns Data/Clock Period Resolution 5.0ns Max Data Pin TG Programmable Range lesser of 4 cycles or 615ns (1) Data Pin TG Resolution 625ps Data Pin Edge Placement Accuracy ± 1.8ns Minimum Pulse Width 5ns Clock rate 50MHz Pattern Memory Vector Memory 32M per pin Capture Memory 16M.