Used TERADYNE / EAGLE ETS 364 #9027189 for sale

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Final Test
Manufacturer
TERADYNE / EAGLE
Model
ETS 364
ID: 9027189
Tester ESMO manipulator Primary Digital Card Cage 1 THIB-PRI 2 QTMU 0-3 3 DPU-16--1 16-31 4 DPU-16--0 0-15 5 CBIT-64 6 MCU 66MHz 7 ISO-COM 64 8 Empty 9 Empty 10 Empty 11 DPU-16--4 64-79 12 DPU-16--3 48-63 13 DPU-16--2 32-47 14 Empty Primary FR Chassis 0 SPU-100 takes 2 slots 1 2 APU-12 0-11 3 0-7 4 APU-12 12-23 5 8-15 6 APU-12 24-35 7 16-23 8 SPU-100 9 10 APU-12 36-47 11 12 APU-12 48-59 13 14 APU-12 60-71 15 16 17 18 QMS 0-1 19 QMS 2-3 20 21 22 23 24 SPU-100 25 26 APU-12 72-83 27 28 APU-12 84-95 29 30 APU-12 96-107 31 32 SPU-100 33 34 APU-12 108-119 35 36 APU-12 120-131 37 38 APU-12 132-143 39 Test head address \0xD000 ////////////////////////////////////////////////////////////////////////////// // Valid Test Head Types: // // 500D, 564, 300, 200, BT2000, 600, 364 // ////////////////////////////////////////////////////////////////////////////// Test head type: \364 Tester Maximum Voltage \maxv \1000 ////////////////////////////////////////////////////////////////////////////// //NOTE: // // All examples use the forward slash '/' instead of the other slash. // // This is so that backward compatibility is maintained. // // // // If you copy the example, please change the forward slash '/' to the // // other slash. // // // ////////////////////////////////////////////////////////////////////////////// // // // Iso-comm Position Mapping Syntax: // // // // Place the logical position number of the floating resource in the // // 'pos' field of the line corresponding to the actual Iso-comm channel. // // If a line is missing or the 'pos' field is left blank, the position // // defaults to direct mapping. // // // // Example: // // // // Iso-comm Channel #0 /icom0 /pos<num> // // // // where: <num> is the logical icom position, 0 to 255 // // // ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // // // Primary Isocomm Card Cage... // // // ////////////////////////////////////////////////////////////////////////////// Iso-comm Channel #0 \icom0 \pos82 Iso-comm Channel #1 \icom1 \pos87 Iso-comm Channel #2 \icom2 \pos0 Iso-comm Channel #3 \icom3 \pos1 Iso-comm Channel #4 \icom4 \pos4 Iso-comm Channel #5 \icom5 \pos5 Iso-comm Channel #6 \icom6 \pos8 Iso-comm Channel #7 \icom7 \pos9 Iso-comm Channel #8 \icom8 \pos2 Iso-comm Channel #9 \icom9 \pos3 Iso-comm Channel #10 \icom10 \pos6 Iso-comm Channel #11 \icom11 \pos7 Iso-comm Channel #12 \icom12 \pos10 Iso-comm Channel #13 \icom13 \pos11 Iso-comm Channel #14 \icom14 \pos14 Iso-comm Channel #15 \icom15 \pos15 Iso-comm Channel #16 \icom16 \pos12 Iso-comm Channel #17 \icom17 \pos13 Iso-comm Channel #18 \icom18 \pos16 Iso-comm Channel #19 \icom19 \pos17 Iso-comm Channel #20 \icom20 \pos20 Iso-comm Channel #21 \icom21 \pos21 Iso-comm Channel #22 \icom22 \pos24 Iso-comm Channel #23 \icom23 \pos25 Iso-comm Channel #24 \icom24 \pos88 Iso-comm Channel #25 \icom25 \pos89 Iso-comm Channel #26 \icom26 \pos90 Iso-comm Channel #27 \icom27 \pos91 Iso-comm Channel #28 \icom28 \pos18 Iso-comm Channel #29 \icom29 \pos19 Iso-comm Channel #30 \icom30 \pos22 Iso-comm Channel #31 \icom31 \pos23 // Next 16 positions are used by 64-channel ISO-COMM boards. Iso-comm Channel #32 \icom32 \pos96 Iso-comm Channel #33 \icom33 \pos97 Iso-comm Channel #34 \icom34 \pos98 Iso-comm Channel #35 \icom35 \pos99 Iso-comm Channel #36 \icom36 \pos100 Iso-comm Channel #37 \icom37 \pos101 Iso-comm Channel #38 \icom38 \pos102 Iso-comm Channel #39 \icom39 \pos103 Iso-comm Channel #40 \icom40 \pos104 Iso-comm Channel #41 \icom41 \pos105 Iso-comm Channel #42 \icom42 \pos106 Iso-comm Channel #43 \icom43 \pos107 Iso-comm Channel #44 \icom44 \pos108 Iso-comm Channel #45 \icom45 \pos109 Iso-comm Channel #46 \icom46 \pos110 Iso-comm Channel #47 \icom47 \pos111 Iso-comm Channel #48 \icom48 \pos28 Iso-comm Channel #49 \icom49 \pos29 Iso-comm Channel #50 \icom50 \pos32 Iso-comm Channel #51 \icom51 \pos33 Iso-comm Channel #52 \icom52 \pos36 Iso-comm Channel #53 \icom53 \pos37 Iso-comm Channel #54 \icom54 \pos80 Iso-comm Channel #55 \icom55 \pos81 Iso-comm Channel #56 \icom56 \pos26 Iso-comm Channel #57 \icom57 \pos27 Iso-comm Channel #58 \icom58 \pos30 Iso-comm Channel #59 \icom59 \pos31 Iso-comm Channel #60 \icom60 \pos34 Iso-comm Channel #61 \icom61 \pos35 Iso-comm Channel #62 \icom62 \pos38 Iso-comm Channel #63 \icom63 \pos39 ////////////////////////////////////////////////////////////////////////////// // // // APU Pin mapping syntax: // // // // Place the logical (mapped) iso-comm position number of the APU in the // // 'pos' field of the line corresponding to the pin numbers which that // // APU board represents. If a line is missing or the 'pos' field is left // // blank, auto-pin assignments will occur for each APU present. // // // // Example: // // // // APU Pin Numbers 0-7 /apu0 /pos<num> // // // // where: <num> is the logical icom position, 0 to 255 // // // ////////////////////////////////////////////////////////////////////////////// APU Pin Numbers 0-7 \apu0 \ APU Pin Numbers 8-15 \apu8 \ APU Pin Numbers 16-23 \apu16 \ APU Pin Numbers 24-31 \apu24 \ APU Pin Numbers 32-39 \apu32 \ APU Pin Numbers 40-47 \apu40 \ APU Pin Numbers 48-55 \apu48 \ APU Pin Numbers 56-63 \apu56 \ APU Pin Numbers 64-71 \apu64 \ APU Pin Numbers 72-79 \apu72 \ APU Pin Numbers 80-87 \apu80 \ APU Pin Numbers 88-95 \apu88 \ APU Pin Numbers 96-103 \apu96 \ APU Pin Numbers 104-111 \apu104 \ APU Pin Numbers 112-119 \apu112 \ APU Pin Numbers 120-127 \apu120 \ APU Pin Numbers 128-135 \apu128 \ APU Pin Numbers 136-143 \apu136 \ APU Pin Numbers 144-151 \apu144 \ APU Pin Numbers 152-159 \apu152 \ APU Pin Numbers 160-167 \apu160 \ APU Pin Numbers 168-175 \apu168 \ APU Pin Numbers 176-183 \apu176 \ APU Pin Numbers 184-191 \apu184 \ APU Pin Numbers 192-199 \apu192 \ APU Pin Numbers 200-207 \apu200 \ APU Pin Numbers 208-215 \apu208 \ APU Pin Numbers 216-223 \apu216 \ APU Pin Numbers 224-231 \apu224 \ APU Pin Numbers 232-239 \apu232 \ APU Pin Numbers 240-247 \apu240 \ APU Pin Numbers 248-255 \apu248 \ ////////////////////////////////////////////////////////////////////////////// // // // APU-12 Pin mapping syntax: // // // // Place the logical(mapped) odd iso-comm position number of the APU-12 in// // the 'pos' field of the line corresponding to the pin numbers which that// // APU-12 board represents. If a line is missing or the 'pos' field is // // left blank, auto-pin assignments will occur for each APU-12 present. // // // // Example: // // // // APU-12 Pin Numbers 0-11 /apu12-pin0 /pos<num> // // where: <num> is the logical icom position, 0 to 255 // // // ////////////////////////////////////////////////////////////////////////////// APU-12 Pin Numbers 0-11 \apu12-pin0 \pos3 APU-12 Pin Numbers 12-23 \apu12-pin12 \pos5 APU-12 Pin Numbers 24-35 \apu12-pin24 \pos7 APU-12 Pin Numbers 36-47 \apu12-pin36 \pos11 APU-12 Pin Numbers 48-59 \apu12-pin48 \pos13 APU-12 Pin Numbers 60-71 \apu12-pin60 \pos15 APU-12 Pin Numbers 72-83 \apu12-pin72 \pos27 APU-12 Pin Numbers 84-95 \apu12-pin84 \pos29 APU-12 Pin Numbers 96-107 \apu12-pin96 \pos31 APU-12 Pin Numbers 108-119 \apu12-pin108 \pos35 APU-12 Pin Numbers 120-131 \apu12-pin120 \pos37 APU-12 Pin Numbers 132-143 \apu12-pin132 \pos39 APU-12 Pin Numbers 144-155 \apu12-pin144 \ APU-12 Pin Numbers 156-167 \apu12-pin156 \ APU-12 Pin Numbers 168-179 \apu12-pin168 \ APU-12 Pin Numbers 180-191 \apu12-pin180 \ APU-12 Pin Numbers 192-203 \apu12-pin192 \ APU-12 Pin Numbers 204-215 \apu12-pin204 \ APU-12 Pin Numbers 216-227 \apu12-pin216 \ APU-12 Pin Numbers 228-239 \apu12-pin228 \ APU-12 Pin Numbers 240-251 \apu12-pin240 \ : : : : : APU-12 Pin Numbers 468-479 \apu12-pin468 \ ////////////////////////////////////////////////////////////////////////////// // // // QMS Pin mapping syntax: // // // // Place the logical (mapped) iso-comm position number of the QMS in the // // 'pos' field of the line corresponding to the pin numbers which that QMS // // icom num represents. If a line is missing or the 'pos' field is left // // blank, auto-pin assignments will occur for each QMS pin present. // // // // Example: // // // // QMS Pin Numbers 8-9 /qms8 /pos<num> // // // // where: <num> is the logical icom position, 0 to 255 // // // ////////////////////////////////////////////////////////////////////////////// QMS Pin Numbers 0-1 \qms0 \pos18 QMS Pin Numbers 2-3 \qms2 \pos19 QMS Pin Numbers 4-5 \qms4 \ QMS Pin Numbers 6-7 \qms6 \ QMS Pin Numbers 8-9 \qms8 \ QMS Pin Numbers 10-11 \qms10 \ QMS Pin Numbers 12-13 \qms12 \ QMS Pin Numbers 14-15 \qms14 \ QMS Pin Numbers 16-17 \qms16 \ QMS Pin Numbers 18-19 \qms18 \ QMS Pin Numbers 20-21 \qms20 \ QMS Pin Numbers 22-23 \qms22 \ QMS Pin Numbers 24-25 \qms24 \ QMS Pin Numbers 26-27 \qms26 \ QMS Pin Numbers 28-29 \qms28 \ QMS Pin Numbers 30-31 \qms30 \ : : : : : QMS Pin Numbers 124-125 \qms124 \ QMS Pin Numbers 126-127 \qms126 \ ////////////////////////////////////////////////////////////////////////////// // // // QHSU Pin mapping syntax: // // // // Place the logical (mapped) iso-comm position number of the QHSU in the // // 'pos' field of the line corresponding to the pin numbers which that QHSU// // icom num represents. If a line is missing or the 'pos' field is left // // blank, auto-pin assignments will occur for each QHSU pin present. // // // // Example: // // // // QHSU Pin Numbers 8-9 /qhsu8 /pos<num> // // // // where: <num> is the logical icom position, 0 to 255 // // // ////////////////////////////////////////////////////////////////////////////// QHSU Pin Numbers 0-1 \qhsu0 \ QHSU Pin Numbers 2-3 \qhsu2 \ QHSU Pin Numbers 4-5 \qhsu4 \ QHSU Pin Numbers 6-7 \qhsu6 \ QHSU Pin Numbers 8-9 \qhsu8 \ QHSU Pin Numbers 10-11 \qhsu10 \ QHSU Pin Numbers 12-13 \qhsu12 \ QHSU Pin Numbers 14-15 \qhsu14 \ QHSU Pin Numbers 16-17 \qhsu16 \ QHSU Pin Numbers 18-19 \qhsu18 \ QHSU Pin Numbers 20-21 \qhsu20 \ QHSU Pin Numbers 22-23 \qhsu22 \ QHSU Pin Numbers 24-25 \qhsu24 \ QHSU Pin Numbers 26-27 \qhsu26 \ QHSU Pin Numbers 28-29 \qhsu28 \ QHSU Pin Numbers 30-31 \qhsu30 \ : : : : : : : : : : : : QHSU Pin Numbers 252-253 \qhsu252 \ QHSU Pin Numbers 254-255 \qhsu254 \ ////////////////////////////////////////////////////////////////////////////// // // // 8x8 Matrix Resource/Channel mapping syntax: // // // // Place the logical (mapped) iso-comm position number of the 8x8 Matrix // // in the 'pos' field of the line corresponding to the Resource/Channel // // numbers which that 8x8 Matrix board represents. If a line is missing // // or the 'pos' field is left blank, resource/channel number assignments // // will occur automatically for each 8x8 Matrix present. // // // // Example: // // // // Matrix Res/Chan Numbers 0-7 /mat0 /pos<num> // // // // where: <num> is the logical icom position, 0 to 255 // // // ////////////////////////////////////////////////////////////////////////////// Matrix Res/Chan Numbers 0-7 \mat0 \ Matrix Res/Chan Numbers 8-15 \mat8 \ Matrix Res/Chan Numbers 16-23 \mat16 \ Matrix Res/Chan Numbers 24-31 \mat24 \ Matrix Res/Chan Numbers 32-39 \mat32 \ Matrix Res/Chan Numbers 40-47 \mat40 \ Matrix Res/Chan Numbers 48-55 \mat48 \ Matrix Res/Chan Numbers 56-63 \mat56 \ Matrix Res/Chan Numbers 64-71 \mat64 \ Matrix Res/Chan Numbers 72-79 \mat72 \ Matrix Res/Chan Numbers 80-87 \mat80 \ Matrix Res/Chan Numbers 88-95 \mat88 \ Matrix Res/Chan Numbers 96-103 \mat96 \ Matrix Res/Chan Numbers 104-111 \mat104 \ Matrix Res/Chan Numbers 112-119 \mat112 \ Matrix Res/Chan Numbers 120-127 \mat120 \ Matrix Res/Chan Numbers 128-135 \mat128 \ Matrix Res/Chan Numbers 136-143 \mat136 \ Matrix Res/Chan Numbers 144-151 \mat144 \ Matrix Res/Chan Numbers 152-159 \mat152 \ Matrix Res/Chan Numbers 160-167 \mat160 \ Matrix Res/Chan Numbers 168-175 \mat168 \ Matrix Res/Chan Numbers 176-183 \mat176 \ Matrix Res/Chan Numbers 184-191 \mat184 \ Matrix Res/Chan Numbers 192-199 \mat192 \ Matrix Res/Chan Numbers 200-207 \mat200 \ Matrix Res/Chan Numbers 208-215 \mat208 \ Matrix Res/Chan Numbers 216-223 \mat216 \ Matrix Res/Chan Numbers 224-231 \mat224 \ Matrix Res/Chan Numbers 232-239 \mat232 \ Matrix Res/Chan Numbers 240-247 \mat240 \ Matrix Res/Chan Numbers 248-255 \mat248 \ ////////////////////////////////////////////////////////////////////////////// // // // QPLU Pin mapping syntax: // // // // Place the logical (mapped) iso-comm position number of the QPLU in the // // 'pos' field of the line corresponding to the pin numbers which that // // QPLU icom num represents. Note that iso-comm positions are shared by // // two consecutive QPLU pins. Therefore only the even pin of the pair // // should be specified in the pin field. If a line is missing or the // // 'pos' field is left blank, auto-pin assignments will occur for each // // QPLU pin present. // // // // Example: // // // // QPLU Pin Numbers 0-1 /qplu0 /pos<num> // // QPLU Pin Numbers 2-3 /qplu2 /pos<num> // // // // where: <num> is the logical icom position, 0 to 255 // // // // // // QPLU Pin-to-CIB mapping syntax: // // // // Place the logical (mapped) CIB cable position number connected to the // // QPLU pin in the 'cib' field of the line corresponding to the QPLU pin. // // Unmapped pins will have no CIB connection assigned. // // // // Note that logical CIB connection mapping is valid offline only. In // // online mode the actual CIB connection is detected automatically. // // // // Example: // // // // QPLU Pin Number 0 \qplu-pin0 \cib<cibnum> // // QPLU Pin Number 1 \qplu-pin1 \cib<cibnum> // // QPLU Pin Number 2 \qplu-pin2 \cib<cibnum> // // QPLU Pin Number 3 \qplu-pin3 \cib<cibnum> // // // // where: <cibnum> is the cable position on the CIB, 0 to 7 // // // ////////////////////////////////////////////////////////////////////////////// QPLU Pin Numbers 0-1 \qplu0 \ QPLU Pin Numbers 2-3 \qplu2 \ QPLU Pin Numbers 4-5 \qplu4 \ QPLU Pin Numbers 6-7 \qplu6 \ QPLU Pin Numbers 8-9 \qplu8 \ QPLU Pin Numbers 10-11 \qplu10 \ QPLU Pin Numbers 12-13 \qplu12 \ QPLU Pin Numbers 14-15 \qplu14 \ QPLU Pin Numbers 16-17 \qplu16 \ QPLU Pin Numbers 18-19 \qplu18 \ QPLU Pin Numbers 20-21 \qplu20 \ QPLU Pin Numbers 22-23 \qplu22 \ QPLU Pin Numbers 24-25 \qplu24 \ QPLU Pin Numbers 26-27 \qplu26 \ QPLU Pin Numbers 28-29 \qplu28 \ QPLU Pin Numbers 30-31 \qplu30 \ : : : : : : QPLU Pin Numbers 78-79 \qplu78 \ QPLU Pin Number 0 \qplu-pin0 \ QPLU Pin Number 1 \qplu-pin1 \ QPLU Pin Number 2 \qplu-pin2 \ QPLU Pin Number 3 \qplu-pin3 \ QPLU Pin Number 4 \qplu-pin4 \ QPLU Pin Number 5 \qplu-pin5 \ QPLU Pin Number 6 \qplu-pin6 \ QPLU Pin Number 7 \qplu-pin7 \ QPLU Pin Number 8 \qplu-pin8 \ QPLU Pin Number 9 \qplu-pin9 \ QPLU Pin Number 10 \qplu-pin10 \ QPLU Pin Number 11 \qplu-pin11 \ QPLU Pin Number 12 \qplu-pin12 \ QPLU Pin Number 13 \qplu-pin13 \ QPLU Pin Number 14 \qplu-pin14 \ QPLU Pin Number 15 \qplu-pin15 \ QPLU Pin Number 16 \qplu-pin16 \ : : : : : : QPLU Pin Number 78 \qplu-pin78 \ QPLU Pin Number 79 \qplu-pin79 \ ////////////////////////////////////////////////////////////////////////////// // // // Internal Cbit Wiring syntax: // // // // Use this section to specify Internal Cbits that are hard wired to a // // resource and cannot be toggled during diagnostics. Any Internal Cbits // // specified in this section will be skipped during Cbit diagnostics. // // The second field can be any user-defined string. // // If a line is missing or the second field is left blank, the Internal // // Cbit will be tested normally during diagnostics. // // // // Example: // // // // Internal Cbit Wiring #0 \icbit0 \RF Cal Board // // // ////////////////////////////////////////////////////////////////////////////// Internal Cbit Wiring #0 \icbit0 \ Internal Cbit Wiring #1 \icbit1 \ Internal Cbit Wiring #2 \icbit2 \ : : : : : Internal Cbit Wiring #31 \icbit31 \ ////////////////////////////////////////////////////////////////////////////// // // // RF3000 -DOWNCONVERTER to QMS Connection: // // // // Place here the QMS pin that connects to the downconverter output // // // // Valid qms<pin>'s are: 0 - 127 // // Example: // // // // RF3000 DOWNCONV /rf3dwncnv /qms4 // // // ////////////////////////////////////////////////////////////////////////////// RF3000 DOWNCONV \rf3dwncnv \ ////////////////////////////////////////////////////////////////////////////// // // // DUAL RF3000 -DOWNCONVERTER to QMS Connections: // // // // Place here the QMS pin that connects to the downconverter output // // // // Valid qms<pin>'s are: 0 - 127 // // Example: // // // // RF3000 DOWNCONV /drf3dwncnv-0 /qms4 // // RF3000 DOWNCONV /drf3dwncnv-1 /qms5 // // // ////////////////////////////////////////////////////////////////////////////// RF3000 DOWNCONV \drf3dwncnv-0 \ RF3000 DOWNCONV \drf3dwncnv-1 \ ////////////////////////////////////////////////////////////////////////////// // // // RF-6000 CONFIGURATION SYNTAX: // // I- Iso-comm position assignment // // II- RF6000 QDC to QHSU connection (Direct or Multiplexed) // // III- SMIQ to QHSU (I/Q) connections // // // // // // Assign two consecutive Iso-comm positions from the // // "MAINFRAME CARD CAGE" group to the RF6000 resources. // // // // Iso-comm assignment Example: // // // // Iso-comm base Resource \ires88 \RF6-SRC // // Iso-comm base Resource \ires89 \RF6-MEAS // // // // // // DIRECT QDC-QHSU CONNECTION EXAMPLE: // // // // rf6 qdc to qhsu connection \rf6qdc-0_0 \qhsu-rf0 // // rf6 qdc to qhsu connection \rf6qdc-0_1 \qhsu-rf1 // // rf6 qdc to qhsu connection \rf6qdc-0_2 \qhsu-rf2 // // rf6 qdc to qhsu connection \rf6qdc-0_3 \qhsu-rf3 // // // // rf6 qdc to qhsu connection \rf6qdc-1_0 \qhsu-rf4 // // rf6 qdc to qhsu connection \rf6qdc-1_1 \qhsu-rf5 // // rf6 qdc to qhsu connection \rf6qdc-1_2 \qhsu-rf6 // // rf6 qdc to qhsu connection \rf6qdc-1_3 \qhsu-rf7 // // // // MUXED QDC-QHSU CONNECTION EXAMPLE: // // // // rf6 qdc to qhsu connection \rf6qdc-mux0-0 \qhsu-rf0 // // rf6 qdc to qhsu connection \rf6qdc-mux0-1 \qhsu-rf1 // // rf6 qdc to qhsu connection \rf6qdc-mux0-2 \qhsu-rf2 // // rf6 qdc to qhsu connection \rf6qdc-mux0-3 \qhsu-rf3 // // // // rf6 qdc to qhsu connection \rf6qdc-mux1-0 \qhsu-rf0 // // rf6 qdc to qhsu connection \rf6qdc-mux1-1 \qhsu-rf1 // // rf6 qdc to qhsu connection \rf6qdc-mux1-2 \qhsu-rf2 // // rf6 qdc to qhsu connection \rf6qdc-mux1-3 \qhsu-rf3 // // // // // // SMIQ QHSU (I/Q) CONNECTION EXAMPLE: // // rf6 iq to qhsu connection \rf6src-0_I \qhsu0 // // rf6 iq to qhsu connection \rf6src-0_Q \qhsu1 // // rf6 iq to qhsu connection \rf6src-1_I \qhsu2 // // rf6 iq to qhsu connection \rf6src-1_Q \qhsu3 // // // ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // // // GPIB mapping syntax: // // // // Place here the GPIB addresses versus system resource mapping // // // // Valid GPIB addresses : gpib-0 to gpib-30 // // Valid resource keywords are: // // RS0, RS1, RS2, LO // // // // Example: // // // // GPIB Address \gpib-27 \RS0 // // GPIB Address \gpib- \RS1 ** not assigned for SMATE** // // GPIB Address \gpib-28 \LO // // // // Please consult ets\inc\gpib500d.h to avoid gpib address conflicts // //
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TERADYNE / EAGLE ETS 364 is a versatile, high-performance, automated final test equipment used for testing and characterizing printed circuit assemblies (PCA). This system is designed to be flexible and easily programmable for the production of high reliability PCBs. EAGLE ETS364 is able to verify a wide variety of devices, including logic, analog, memory, MCU's, and RF transceivers. It includes several features to help ensure the highest quality test results, such as: an illumination unit to support defect analysis, software report generation, an alarm machine to detect faulty test data, and a whole-board test tool (WBTS) to perform in-circuit tests. TERADYNE ETS-364 also comes with a programmable time-delay-on-fail trigger and adjustable test temperature ranges to better control the test parameters. Additionally, TERADYNE / EAGLE ETS-364 is also equipped with on-board diagnostics, a scan-chain test controller, and a scan-inbound digital pattern. EAGLE ETS-364 features tight integration of test asset hardware, test strategies, power control capabilities, and signal generator. This enables the operator to easily and quickly measure PDFs, JEDECs, Flash, Path Lengths, Digital Pattern, and Impedance Tests. The test model utilizes programmable power supplies and external 3-phase power supplies to provide stable voltage levels, ensuring accuracy and repeatability. Furthermore, ETS-364 also provides a full suite of options for writing or editing test software and test programs, as well as test results storage and test adaptability to customer-specific needs. TERADYNE ETS364 is a multi-function machine that not only performs the necessary tests but also prints and interprets the test results. This ensures that the test results are accurate, repeatable, and reproducible. Additionally, the powerful data acquisition and analysis equipment allows for easy access to key test data points for advanced statistical analysis. TERADYNE ETS 364 is an easy-to-use and reliable automated final test system that is designed to help improve throughput, reduce manufacturing cost, and ensure the highest quality of PCBs. With its comprehensive suite of capabilities, and the ability to be customized to suit any requirement, ETS 364 gives organizations the confidence that their production is reliable and effective.
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