Used TEL / TOKYO ELECTRON P-8 #9384603 for sale

TEL / TOKYO ELECTRON P-8 is a prober used to detect physical properties of semiconductor wafers and devices, including contact resistance, capacitance, and inductance. It is typically used in wafer-level testing and can be used to validate a number of parameters including electrode spacing, line width, coplanarity and lithographic accuracy. TEL P8 is a highly accurate automated prober equipment designed to measure device parameters at the wafer level. In order to accurately measure electrical characteristics such as resistance and dielectric constants, the surface of the wafer must remain clean and dry. To achieve this, TOKYO ELECTRON P 8 uses a high-grade vacuum system to prevent the introduction of moisture, particles and debris from the environment. This ensures that the surface of the wafer before probing is kept as clean as possible. The unit is also equipped with an advanced positioning machine, which is used to create an exact location for each pad on the wafer being tested. This is achieved by continuously monitoring the position of the wafer and prober using precision laser detectors. This high-resolution positioning tool is highly precise, allowing for repeatable measurement of electrical characteristics and other device parameters observed at the wafer level. The asset utilizes a high-precision programmable X/Y platform that enables a controlled and stable approach to the wafer. The mechanically stable platform also provides the operator with full control over every aspect of the probe process. In addition, TEL P-8 includes a set of digital multi-meter devices and probes that are used to measure various electrical characteristics of the wafer. This allows for the accurate measurement of contact resistance, capacitance, and inductance. The combination of high-precision positioning, a clean environment in which to measure, and precision multi-meters allows TOKYO ELECTRON P8 to produce highly accurate results in a very short time. As a result, P-8 is an invaluable tool for wafer-level testing requirements.